1. Technical Field of the Invention
This disclosure relates to methods of manufacturing a semiconductor device and semiconductor devices fabricated using the same and, more particularly, to self-aligned trench isolation methods of a semiconductor device that employs at least two gate insulating layers having different thickness and semiconductor devices manufactured using the same.
2. Description of the Related Art
Semiconductor devices include discrete devices such as transistors. Isolation techniques are used in order to separate the transistors.
Recently, a trench isolation technique has been widely used. In particular, a self-aligned trench isolation technique is broadly used in fabrication of semiconductor memory devices such as flash memory devices in order to improve characteristics of flash memory cells.
Semiconductor memory devices such as the flash memory devices may include a cell array region and a peripheral circuit region. The cell array region may include a plurality of cell transistors arranged in a two-dimensional array, and the peripheral circuit region may include high voltage transistors and low voltage transistors. In flash memory devices, each of the cell transistors typically has a stacked gate pattern, which is composed of a tunnel oxide layer, a floating gate, an inter-gate insulating layer, and a control gate electrode that are sequentially stacked. Also, the high voltage transistor employs a gate insulating layer which is thicker than the tunnel oxide layer. Accordingly, there may be some limitations in applying the self-aligned trench isolation technique to the flash memory devices.
A method of fabricating the flash memory device using the self-aligned trench isolation technique is taught in U.S. Patent Publication No. US 2002/0016041 A1 to Boo et al., entitled “Method Of Fabricating A Non-Volatile Memory Device Having A Tunnel Insulating Layer Including More Than Two Portions Of Different Thickness”.
According to Boo et al., a tunnel insulating layer and a gate insulating layer thicker than the tunnel insulating layer are formed on a cell array region and a peripheral circuit region of a semiconductor substrate, respectively. A conductive layer and a first insulating layer are sequentially formed on the entire surface of the semiconductor substrate having the tunnel insulating layer and the gate insulating layer. The first insulating layer, the conductive layer, the tunnel insulating layer, the gate insulating layer, and the semiconductor substrate are dry-etched to form a trench region that defines active regions. In this case, a sidewall of the trench region generally exhibits a positive sloped profile due to characteristics of the dry etching process. In other words, an upper width of the trench region is greater than the lower width thereof. An isolation layer is then formed in the trench region. As a result, a sidewall of the isolation layer has a negative sloped profile.
The first insulating layer is removed to expose the conductive layer. As a result, the isolation layer is relatively protruded. A protrusion of the isolation layer also has a negative sloped profile. Hence, in the event that the conductive layer is patterned to form floating gate patterns separated from each other in the cell array region in a subsequent process, stringers may exist between the floating gate patterns. In order to solve the problem described above, Boo et al. use a chemical mechanical polishing (CMP) technique to remove the protrusion from the isolation layer.
Notwithstanding the removal of the protrusion from the isolation layer, the self-aligned trench isolation technique described above has several disadvantages.
FIGS. 1 to 8 are cross-sectional diagrams illustrating a conventional self-aligned trench isolation method in conjunction with a flash memory device.
Referring to FIG. 1, a gate insulating layer 3, a lower gate conductive layer 5 and a gate etching stopper layer 7 are sequentially formed over the entire surface of a semiconductor substrate 1. The gate etching stopper layer 7, the lower gate conductive layer 5 and the gate insulating layer 3 are patterned to expose a predetermined region of the semiconductor substrate 1. The exposed region of the semiconductor substrate 1 corresponds to a cell array region A, and the region covered with the patterned gate etching stopper layer 7 corresponds to a peripheral circuit region B. A tunnel oxide layer 9, a conductive layer 11 and a hard mask layer 13 are sequentially formed on the resultant structure where the semiconductor substrate 1 in the cell array region A is exposed.
A first photoresist pattern 15 is formed on the hard mask layer 13. The first photoresist pattern 15 is formed to cover an adjacent region to the cell array region A as well as the cell array region A with consideration of mis-alignment occurred during a photolithography process. As a result, an edge of the first photoresist pattern 15 overlaps with an edge of the patterned gate etching stopper layer 7 as shown in FIG. 1. Thus, a border region D composed of the overlapping region between the cell array region A and the peripheral circuit region B is defined.
Referring to FIG. 2, the hard mask layer 13 is etched using the first photoresist pattern 15 as an etching mask to form a hard mask pattern 13a that covers the cell array region A and the border region D. The first photoresist pattern 15 is then removed. The conductive layer 11 is etched using the hard mask pattern 13a as an etching mask to form a lower floating layer a below the hard mask pattern 13a. 
Referring to FIG. 3, the hard mask pattern 13a and the gate etching stopper layer 7 are blanket-etched to expose the lower floating gate layer 11a and the lower gate conductive layer 5. As a result, a gate etching stopper layer pattern 7a exists in the border region D. The gate etching stopper layer pattern 7a is interposed between the lower gate conductive layer 5 and the lower floating gate layer 11a. 
A buffer oxide layer 17, a CMP stopper layer 19 and a hard mask layer 21 are sequentially formed over the entire surface of the semiconductor substrate 1 where the lower floating gate layer 11a and the lower gate conductive layer 5 are exposed. A second photoresist pattern 23 is formed on the hard mask layer 21. The second photoresist pattern 23 includes a cell active pattern 23a and a peripheral circuit active pattern 23b that define a cell active region and a peripheral circuit active region in the cell array region A and the peripheral circuit region B, respectively. The peripheral circuit active pattern 23b is formed to cover a portion of the border region D. This prevents the chip size of the semiconductor device from increasing.
Referring to FIG. 4, the hard mask layer 21, the CMP stopper layer 19, and the buffer oxide layer 17 are successively patterned using the second photoresist pattern 23 as an etching mask. As a result, a first trench mask pattern covering a predetermined portion in the cell array region A is formed, and a second trench mask pattern covering an edge portion of the peripheral circuit region B and an edge portion of the border region D is formed. The first trench mask pattern includes a first buffer oxide layer pattern 17a, a first CMP stopper layer pattern 19a and a first hard mask pattern 21a which are sequentially stacked, and the second trench mask pattern includes a second buffer oxide layer pattern 17b, a second CMP stopper layer pattern 19b and a second hard mask pattern 21b which are sequentially stacked. The second photoresist pattern 23 is then removed.
Referring to FIG. 5, the tunnel oxide layer 9 and the gate insulating layer 3 as well as the lower floating gate layer 11a and the lower gate conductive layer 5 are etched using the first and second trench mask patterns as etching masks. As a result, a tunnel oxide layer pattern 9a and a lower floating gate pattern 11b which are sequentially stacked below the first trench mask pattern are formed, and a gate insulating layer pattern 3a and a lower gate electrode pattern 5a which are sequentially stacked below the second trench mask pattern are formed. In addition, the gate etching stopper layer pattern 7a and a conductive layer pattern 11c composed of a portion of the lower floating gate layer 11a remain between the lower gate electrode pattern 5a and the second trench mask pattern.
Referring to FIG. 6, the semiconductor substrate 1 is etched using the first and second trench mask patterns as etching masks to form a trench region 25. As a result, a cell active region 25a is defined in the cell array region A and a guard band active region 25d is defined in the border region D and an edge of the peripheral circuit region B.
Referring to FIGS. 7 and 8, an insulating layer is formed on the entire surface of the semiconductor substrate 1 having the trench region 25. The insulating layer is planarized until the first and second CMP stopper layer patterns 19a and 19b are exposed, thereby forming an isolation layer 27 in the trench region 25. Subsequently, the CMP stopper layer patterns 19a and 19b and the buffer oxide layer patterns 17a and 17b are removed to expose the lower floating gate pattern 11b and the lower gate electrode pattern 5a. The CMP stopper layer patterns 19a and 19b and the buffer oxide layer patterns 17a and 17b are removed using a wet etching technique in order to prevent surfaces of the lower floating gate pattern 11b and the lower gate electrode pattern 5a from being damaged. When the CMP stopper layer patterns 19a and 19b and the buffer oxide layer patterns 17a and 17b are excessively wet-etched, the conductive layer pattern 11c in the border region D may be lifted off. In particular, as the semiconductor devices become more highly integrated, a width of the conductive layer pattern 11c has been reduced. In this case, the conductive layer pattern 11c may be easily lifted off.
Meanwhile, in order to prevent the conductive layer pattern 11c from being lifted off, a wet-etching process time should be reduced. In this case, as shown in FIG. 8, the gate etching stopper layer pattern 7a may exist on the lower gate electrode pattern 5a in the border region D. Hence, the lower gate electrode 5a in the border region D may not be removed in a subsequent process. Consequently, it is not possible to dope the guard band active region 25d with impurity ions through a conventional semiconductor manufacturing process. In other words, it is impossible to form an impurity region such as a well pick up region in the guard band active region 25d. Hence, the guard band active region 25d in the border region D loses its inherent function, thereby increasing a chip size.
Embodiments of the invention address these and other disadvantages of the conventional art.